JPS622349B2 - - Google Patents

Info

Publication number
JPS622349B2
JPS622349B2 JP12925282A JP12925282A JPS622349B2 JP S622349 B2 JPS622349 B2 JP S622349B2 JP 12925282 A JP12925282 A JP 12925282A JP 12925282 A JP12925282 A JP 12925282A JP S622349 B2 JPS622349 B2 JP S622349B2
Authority
JP
Japan
Prior art keywords
circuit
command
data transfer
channels
control unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP12925282A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5920031A (ja
Inventor
Shuji Hisanaga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP12925282A priority Critical patent/JPS5920031A/ja
Publication of JPS5920031A publication Critical patent/JPS5920031A/ja
Publication of JPS622349B2 publication Critical patent/JPS622349B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
JP12925282A 1982-07-23 1982-07-23 デ−タ転送装置 Granted JPS5920031A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12925282A JPS5920031A (ja) 1982-07-23 1982-07-23 デ−タ転送装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12925282A JPS5920031A (ja) 1982-07-23 1982-07-23 デ−タ転送装置

Publications (2)

Publication Number Publication Date
JPS5920031A JPS5920031A (ja) 1984-02-01
JPS622349B2 true JPS622349B2 (en]) 1987-01-19

Family

ID=15004966

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12925282A Granted JPS5920031A (ja) 1982-07-23 1982-07-23 デ−タ転送装置

Country Status (1)

Country Link
JP (1) JPS5920031A (en])

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62247443A (ja) * 1986-03-20 1987-10-28 Fujitsu Ltd チヤネル制御方式

Also Published As

Publication number Publication date
JPS5920031A (ja) 1984-02-01

Similar Documents

Publication Publication Date Title
US4435755A (en) Balanced channel finding method
US5201053A (en) Dynamic polling of devices for nonsynchronous channel connection
JPH06266649A (ja) 複数のデータチャネルを介してデータを転送する方法及びその回路アーキテクチャ
JPH06266650A (ja) データを転送する方法と装置及びデータ転送をインタリーブする装置
JPH0650493B2 (ja) データ処理装置
KR20080105390A (ko) 플래시 메모리에 사용되는 명령어들을 제어하는 방법 및장치
US3961312A (en) Cycle interleaving during burst mode operation
EP0055623B1 (en) Direct memory-access mode for a high-speed memory system
US6282144B1 (en) Multi-ported memory with asynchronous and synchronous protocol
JPS622349B2 (en])
US3248701A (en) Data transfer control system
KR920007949B1 (ko) 컴퓨터 주변장치 제어기
JPH0962633A (ja) ネットワーク制御装置
JPS6240736B2 (en])
JPH08249269A (ja) Ｄｍａ転送制御方法及びｄｍａ転送制御装置
JPS63132362A (ja) コマンド動作制御方式
JPH0736806A (ja) Ｄｍａ方式
JPS59225426A (ja) 入出力制御装置
JPH0424733B2 (en])
JPH05204830A (ja) 入出力制御装置
JPS6126703B2 (en])
JPH0130170B2 (en])
JPH0492936A (ja) メモリアクセス制御装置
JPH0954743A (ja) チャネル装置
JPS6186859A (ja) バス選択装置